The logical operators and, or, nand, nor, xor, xnor and not take operands that must be Boolean values, and they produce Boolean results. Composite Resolved Subtypes 8. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. Summary of Resolved Subtypes 8.
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In the course of this program, it became clear that there was a need for a standard language for describing the structure and function of integrated circuits ICs. This first standard version of the language is often referred to as VHDL Comments and suggestions from users of the standard were analyzed by the IEEE working group responsible for VHDL, and in a revised version of the standard was proposed.
This was eventually adopted in , giving us VHDL A second round of revision of the standard was started in That process was completed in , giving us VHDL After that, further development took place in the IEEE working group and in a technical committee of an organization, Accellera, whose charter is to promote standards for electronics design. These efforts led to the current version of the language, VHDL, described in this book.
VHDL is designed to fill a number of needs in the design process. First, it allows description of the structure of a system, that is, how it is decomposed into subsystems and how those subsystems are interconnected. Second, it allows the specification of the function of a system using familiar programming language forms. Third, as a result, it allows the design of a system to be simulated before being manufactured, so that designers can quickly compare alternatives and test for correctness without the delay and expense of hardware prototyping.
Fourth, it allows the detailed structure of a design to be synthesized from a more abstract specification, allowing designers to concentrate on more strategic design decisions and reducing time to market. This book presents a structured guide to the modeling facilities offered by the VHDL language, showing how they can be used for the design of digital systems.
The book does not purport to teach digital design, since that topic is large enough by itself to warrant several textbooks covering its various aspects. Instead, the book assumes that the reader has at least a basic grasp of digital design concepts, such as might be gained from a first course in digital design in an engineering degree program.
Some exposure to computer programming and to concepts of computer organization will also be beneficial. This book is suitable for use in a course in digital or computer design and will also serve practicing engineers who need to acquire VHDL fluency as part of their changing job requirements. One pervasive theme running through the presentation in this book is that modeling a system using a hardware description language is essentially a software design exercise.
This implies that good software engineering practice should be applied. Hence the treatment in this book draws directly from experience in software engineering. There are nuxvii xviii Preface merous hints and techniques from small-scale and large-scale software engineering presented throughout the book, with the sincere intention that they might be of use to readers.
I am particularly pleased to be able to include this book in the Morgan Kaufmann Series in Systems on Silicon. Modeling for simulation and synthesis is a vital part of a design methodology for large-scale systems.
VHDL allows models to be expressed at a range of levels of abstraction, from gate-level up to algorithmic and architectural levels. It will continue to play an important role in the design of silicon-based systems for some time to come.
This path offers a graduated development, with each chapter building on ideas introduced in the preceding chapters. Each chapter introduces a number of related concepts or language facilities and illustrates each one with examples. Scattered throughout the book are three case studies, which bring together preceding material in the form of extended worked examples.
Chapter 1 introduces the idea of a hardware description language and outlines the reasons for its use and the benefits that ensue. It then proceeds to introduce the basic concepts underlying VHDL, so that they can serve as a basis for examples in subsequent chapters.
The next three chapters cover the aspects of VHDL that are most like conventional programming languages. These may be used to describe the behavior of a system in algorithmic terms. Chapter 2 explains the basic type system of the language and introduces the scalar data types.
Chapter 3 describes the sequential control structures, and Chapter 4 covers composite data structures used to represent collections of data elements. These include facilities for modeling the basic behavioral elements in a design, the signals that interconnect them and the hierarchical structure of the design.
The next group of chapters extends this basic set of facilities with language features that make modeling of large systems more tractable. Chapter 6 introduces procedures and functions, which can be used to encapsulate behavioral aspects of a design.
Chapter 7 introduces the package as a means of collecting together related parts of a design or of creating modules that can be reused in a number of designs. Chapter 8 deals with the important topic of resolved signals, and Chapter 9 describes a number of predefined and standard packages for use in VHDL designs.
The third group of chapters covers advanced modeling features in VHDL. Chapter 11 covers aliases as a way of managing the large number of names that arise in a large model. Chapter 12 describes generics as a means of parameterizing the behavior and structure of a design and enhancing the resusability of designs.
This leads to a discussion of abstract data types as a means of managing the complexity associated with large designs. Chapter 13 deals with the topics of component instantiation and configuration. These features are important in large real-world models, but they can be difficult to understand.
Hence this book introduces structural modeling through the mechanism of direct instantiation in ear- xix Preface lier chapters and leaves the more general case of component instantiation and configuration until this later chapter. In Chapter 14, generated regular structures are covered. The fourth group of chapters covers language facilities generally used for system-level modeling. Chapter 15 introduces the notion of access types or pointers and uses them to develop linked data structures.
The topic of abstract data types is revisited in the context of container data types. Chapter 16 covers the language facilities for input and output using files, including binary files and text files. Chapter 17 is a case study in which a package for designing memories is developed. The package draws upon features described in the third and fourth groups of chapters.
In the fifth group of chapters, we introduce language features for advanced design and verification. Chapter 18 deals with features for test bench support and verification.
Chapter 19 covers protected types and their use as a means of concurrency control. Chapter 20 describes how we can annotate items in a design with attributes to specify information to be used by design automation tools. This leads into Chapter 21, which covers guidelines for writing synthesizable models. This group of chapters is drawn together in a further case study, Chapter 22, showing development of a synthesizable processor core and its use in a small embedded system, a digital alarm clock.
The final chapter, Chapter 23, is a miscellany of advanced topics not covered in the previous chapters. It includes a discussion of blocks and guarded signals, which are not as widely used in modern designs as previously.
Nonetheless, we describe them here for completeness. Each chapter in the book is followed by a set of exercises designed to help the reader develop understanding of the material. Where an exercise relates to a particular topic described in the chapter, the section number is included in square brackets. The remaining categories involve developing VHDL models. Readers are encouraged to test correctness of their models by running them on a VHDL simulator.
This is a much more effective learning exercise than comparing paper models with paper solutions. The second edition was updated to reflect the changes in VHDL Many of the xx Preface changes in the language standard corrected ambiguities in the previous standard that caused incompatibility between VHDL tools from different vendors. There were also changes that enhanced the usability of the language.
The text and examples in the second edition were revised where necessary to reflect the changes in the language. Furthermore, following publication of the first edition, a number of VHDL-related standards were published and gained widespread acceptance. The second edition added descriptions of the IEEE VHDL also specifies numerous minor new features and changes to existing features to enhance the usability of the language.
This edition integrates descriptions of all of the new and revised features into the text. In addition, some of the material has been removed or rearranged. The case study on a package for arithmetic on bit-vector operands has been deleted because the standard numeric packages have now become widespread. The first case study in this book is a revised version of the MAC case study in previous editions, and shows how the standard packages can be used.
The chapter on blocks and guarded signals has been contracted and moved to a section in the last chapter, since the features are now little used in practice. There is a greater emphasis on synthesis in this edition.
What was an appendix on the topic in previous editions has been substantially revised and promoted to full chapter status. The large case study showing development of a bit processor model has been revised to show a smaller synthesizable model of an 8-bit microcontroller core and its use in an embedded system. This is much more relevant, both for educational purposes and professional practice. Finally, this edition includes a listing of all of the VHDL standard packages as an appendix for reference.
Resources for Help and Information Although this book attempts to be comprehensive in its coverage of VHDL, there will no doubt be questions that it does not answer.
For these, the reader will need to seek other resources. User groups generally hold regular meetings that either formally or informally include a time for questions and answers. Many also run e-mail lists and on-line discussion groups for problem solving. Readers who have access to the Usenet electronic news network will find the news group comp. This discussion group is a source of announcements, sample models, questions and answers and useful software.
It is archived at www. However, since it is a definitional document, not a tutorial, it is written in a complex legalistic style. This makes it very difficult to use to answer the usual questions that arise when writing VHDL models. It should only be used once you are somewhat familiar with VHDL. It can be ordered from the IEEE at standards.
This book contains numerous examples of VHDL models that may also serve as a resource for resolving questions. The VHDL source code for these examples and the case studies, as well as other related information, is available on the companion website for the book at books. Although I have been careful to avoid errors in the example code, there are no doubt some that I have missed.
Ashenden,P - The Designer's Guide to VHDL.pdf
I am grateful to the many engineers, stu- dents and teachers around the world who gave me the impetus to write these books and who made them such a success. I hope this new edition will continue to meet the need for a comprehensive guide to VHDL. I remain grateful to all of these people and organizations for their valuable contributions to the earlier editions and to this edition. Much of the material from that book has found its way into this book in one form or another. Thanks also to Mentor Graphics Cor- xxii Preface poration for continued use of the ModelSim simulator to check the example code. I con- tinue to enjoy an excellent working relationship with the staff at Morgan Kaufmann Publishers and their parent company, Elsevier. I remain deeply grateful for her continued sup- port and am honored to also dedicate this third edition to her.
The Designer's Guide to VHDL